1. Field of the Invention
The present invention generally relates to the evaluation of circuit designs and more particularly to an improved method of determining mutual inductance of wires in an electronic design.
2. Description of the Related Art
With today's fast off chip signal switching speed, signal integrity analysis is very important. Simulation with accurate integrated circuit (IC) package signal to signal mutual inductance is very critical to the analysis, and the same is true for (printed circuit boards) PCB. Conventional systems sometimes used a slow, expensive, yet highly accurate electromagnetic (EM) field solver to determine the mutual inductance between or connected to wires on the chip. This conventional system has many sophisticated features to account for the different non-linear shapes of the wires, their distances, etc. However, using an EM field solver to generate mutual inductance is very time consuming and computer resource intensive and not practical for a large number of nets.
The conventional method requires the input of the geometry of the signal traces and power plane structure into the electromagnetic (EM) field solver to generate the mutual inductances. This method is very accurate, but is also very time consuming and difficult to setup when there are hundreds or thousands of nets. Therefore, there is a need for an improved method of determining mutual inductance that avoids the time and cost associated with conventional techniques. The invention described below provides such a methodology.